Programmable logic devices (PLDs) are integrated circuits typically comprised of discrete logic resource units which are user configurable. Each logic resource unit may contain, for example, one or more function generators and one or more storage devices (flip-flops or latches) with some logic between the function generators and the storage devices. Function generators have a fixed number of input terminals and one output terminal. Function generators can be programmed to implement any arbitrarily defined Boolean function of their input signals. Commonly, a function generator is implemented by a look up table within a memory unit. Function generators may also be programmed to implement random access memory (RAM).
Typically, these logic resource units are repeated regularly over the integrated circuit and are surrounded by some specialized programmable discrete input/output (I/O) units for processing signals coming into and out of the integrated circuit. I/O units typically provide for buffering, storage and inversion of signals entering or leaving the PLD. Routing resources are disposed over the entire chip and pass at intervals through programmable interconnect points (PIPs). The usual goal in the placement of routing resources and programmable interconnects is to maximize design flexibility, i.e. maximize the number of different designs which can be placed on the integrated circuit.
Prior art PLDs are designed to accommodate the maximum number of designs, while still providing acceptable speed and size. Because of the character of pipelined designs, using a PLD of the prior art to implement a pipelined design is difficult.
Pipelining is a design implementation technique in which multiple samples of time varying data are processed simultaneously by overlapping operations. In pipelining, individual operations are broken into small steps, or pipe stages. The stages are lined up in time to form a pipeline. Data samples enter at one end, are processed through the stages, and exit at the other end. At any given clock cycle, different pipe stages operate simultaneously on different data samples. Although individual operations may take longer to complete, pipelining increases throughput, i.e. the rate at which data can be processed, or instructions per time period.
To achieve the pipeline of discrete instruction stages, it is typically necessary in custom designed circuits to hold intermediate process results, or stage results, in registers so that data flowing through the pipeline is synchronized, usually to a common clock reference. Accordingly, a typical architecture has at least one register at both the input terminal and output terminal of the logic stage which performs each stage operation. Moreover, the placement of routing resources "follows" the pipeline. As a rule, storage elements (flip-flops or latches) do not need to be supplied with the logic to synchronize data because synchronization between stages is provided by the above-referenced registers. Prior art PLDs are not designed to provide this kind of functionality.
First, the ratio of registers to function generators is typically too low for pipelined designs to be easily accommodated. For example, when providing a pipeline operation, especially in large data widths such as 32 bits or more, data and control signals must be synchronized to their appropriate function generators. The same is true with respect to carry signals. Specifically, carry signals must be pipelined along with the sum data signals output from function generators. The number of shift registers and their placement in prior art programmable logic designs do not readily accommodate these requirements.
Second, a conventional PLD provides extensive routing resources. Many of these routing resources are not necessary for a pipelined design because in a pipelined design data flow is predictable along the pipeline path. Therefore, routing resources of a typical conventional PLD are wasted when implementing a pipelined design.
Additionally, the flip-flops and latches within logic resource units in prior art PLDs typically include logic to handle potential timing problems associated with unsynchronized data. This logic is largely not required by a pipelined design because the data traveling from stage to stage is synchronized by the registers between stages.
Third, clock speed is usually low in a prior art PLD in comparison to the clock speed which is desired in a pipelined design. A conventional PLD lacks the register resources and connectivity to realize higher clock speeds. For example, the conventional architecture may not allow logic resources implementing consecutive pipe stages to be placed contiguously, thus requiring signals between stages to travel long distances. For these reasons, the high clock speed (throughput) which is the goal of pipelining cannot be readily achieved in these architectures.
Therefore, a need arises for a PLD which allows optimal usage of integrated circuit resources for pipelined designs, allows optimal placement of pipelined designs, and realizes pipelined designs with a higher clock speed than possible with typical PLDs. Additionally, a need arises for dedicated shift register paths for pipelined carry signals and pipelined control signals in a pipelined operation, and for synchronized mechanisms for data, control and carry signals in a pipelined format.